~ Abdelrahman H. 9/2015 ~ SoC Encounter is an automatic place and route software from Cadence. 1 Environment Setup and starting Cadence SoC Encounter. Looking around you. Looking around you'll likely see a lot of information about the new Encounter. SoC-Encounter 8.

~ Abdelrahman H. 9/2015 ~ SoC Encounter is an automatic place and route software from Cadence. 1 Environment Setup and starting Cadence SoC Encounter The objective of this section is to learn how to get the environment ready for the tool, take care of the licensing issues, and start the tool. 1.1 SoC Encounter working Directory In your Cadence tools directory, created in, descend into a folder called “PnR”. This folder will be the working directory for the Cadence SoC Encounter. 1.2 Get the needed files ready To start the place and route (PnR) process you will need to provide the following files: • The mapped Verilog file (Output from RTL Compiler). Copy it to /PnR/in • The Output ‘SDC’ file from RTL Compiler Copy it to /PnR/in • Locate the ‘.lib’ timing files.

The.lib files include the needed information about the standard cells. The path: /CMC/kits/AMSKIT616_GPDK/tech/gsclib045_all_v4.4/gsclib045/timing Needed files: “fast_vdd1v0_basicCells.lib” and “slow_vdd1v0_basicCells.lib” • Locate the ‘.lef’ files. Modo For Solidworks Kit Rapidshare there.

The.lef files include the needed layout information about the standard cells. The path: /CMC/kits/AMSKIT616_GPDK/tech/gsclib045_all_v4.4/gsclib045/lef Needed files: “gsclib045_tech.lef”, “gsclib045_multibitsDFF.lef” and “gsclib045_macro.lef” • Download “MMMC.tcl” [Piazza] Contains the timing configurations. Make sure to edit it to point to your SDC file. Copy it to /PnR/in • Download.map and.layermap files [Piazza] Map the layers when importing the design from SoC encounter to Virtuoso. Copy it to /PnR/in 1.3 Source the setup file and run SoC Encounter In the working directory source the provided Setup file. Sourcing this file will take care of all the needed environment variables, and all the licensing as well. After sourcing the setup file, launch the tool.

>>source./setup_local.csh >>encounter -64 -log Mylog After running the previous lines Encounter should open its main window as in Figure 1. Read the log in the terminal to make sure that everything went well with no error. Figure 1 Encounter’s main window 2 Place and Route the design In this section follow the steps to convert your synthesized Verilog file into a layout.

2.1 Design import In this step you will be configuring the tool and loading your design. Go to Import design.

The Design import screen shown in Figure 2 will open. Fill in the fields as follows: Netlist: Select Verilog and browse to your mapped.v file, and Set the name of your Top cell. Technology/Physical Libraries: Select LEF Files and browse to “add” the.lef files mentioned previously. Make sure to add them in order one by one as shown in Figure 3. Power: Set the power and ground nets to VDD and VSS, respectively.

Analysis Configuration: Add your modified “MMMC.tcl”. Kassanna - Scar - .epub on this page. Finally save this configuration, and press OK. Note the change in Encounter’s main window.

Figure 3 Add.lef files 2.2 Floorplan In this step you will select the dimensions of your Layout, the utilization, and the IO ring space. Go to Specify Floorplan. The Specify floorplan window shown in Figure 4 will open. Specify your desired parameters. Note that as you increase the Core utilization your design will have smaller area but this will make it more difficult for the routing tool to accomplish a clean routing with no LVS errors.

Press Ok and notice the change in Encounter’s main window. Figure 4 Specify Floorplan window 2.3 Save design It is beneficial to save your design after each step, in case you want to start again from a specific point instead of repeating the whole process from the beginning. To do so, go to Save Deign>and select the data type to be Encounter. 2.4 Power Planning In this step you will be designing the power distribution network (PDN) for your design. The PDN should be designed in a way that provides power connection to each cell with minimum IR drop. 2.4.1 Power Rings In this step you will create VDD and VSS ring that will surround your deign. Go to Power Planning ->Add Ring.

This will open the Add Rings window shown in Figure 5. In the Net(s) field add VDD and VSS and pick your desired ring configuration settings. Figure 5 Add Power Rings 2.4.2 Power Stripes In this step you will complete the PDN by adding VDD and VSS stipes that will cover the whole PnR area. First go to Special Route>in the SRoute window shown in Figure 6 add VDD and VSS to the Net(s) field and press ok. Then, if needed, you can add more vertical connections to your PDN.